岗位信息
JOB Description:
1. Create verification plan, working with Design Engineer and understand system/customer requirements;
2. Write test cases, stimulus, and checkers;
3. Create/unit-test models for analog blocks.
4. Verify the full product at chip-level, using mixed signal tools.
1. 与设计工程师合作，制定验证计划，了解系统/客户要求；
2. 编写测试cases, stimulus和 checkers；
3. 为模拟blocks创建/ unit-test模型。
4. 使用混合信号工具在芯片级验证完整产品。
Requirements:
1. MSc degree in Microelectronic Major or related area. Have at least 2-3 of working experience on analog/Digital design/verification area;
2. Knowledge of analogue circuit design, digital design, semiconductor devices and Cadence Virtuoso tools
3. Familiar with system-verilog/UVM, Verilog_A or Verilog-AMS
4. Capable of working in a multi-culture environment, communications skills, Good writing and oral skill in English and Chinese.
1. 微电子或相关硕士学位。至少2-3年模拟/数字设计/验证方面的工作经验；
2. 具备模拟电路设计、数字设计、半导体器件和Cadence Virtuoso工具的相关知识；
3. 熟悉system-verilog/UVM、verilog_A或verilog AMS；
4. 能够在多元文化环境中工作，沟通能力强，良好的中英文书面和口语能力。
